1. Technical Field
The present invention relates to a solid-state image sensing apparatus and a method of manufacturing the same and, more particularly, to a solid-state image sensing apparatus formed by bonding a plurality of members including a first member and a second member, and a method of manufacturing such an apparatus.
2. Related Background Art
As solid-state image sensing apparatuses, CCD image sensors and CMOS image sensors are widely used. In a solid-state image sensing element, along with a great increase in pixel density, the occupation ratio of interconnections and transistors serving as switches in each pixel increases. The ratio (aperture ratio) of the light-receiving area decreases, and accordingly, the light-receiving sensitivity becomes low. To avoid this problem, there is employed a technique for mounting a microlens in each pixel or a technique for decreasing the interconnection ratio by using a micropatterning process.
One of application purposes of a solid-state image sensing element is a retina chip. For this application purpose, an advanced function for processing input information for each pixel or high-speed processing is required. Since a memory and a signal processing circuit are added to each pixel, the aperture ratio further decreases. A promising measure against this problem is thought to be employing a so-called three-dimensional circuit element structure in which a solid-state image sensing element and a control processing circuit are stacked.
A prior-art reference about a three-dimensional circuit element is Japanese Patent Laid-Open No. 11-17107. A three-dimensional circuit element manufacturing method described in Japanese Patent Laid-Open No. 11-17107 includes steps of forming a porous layer on a semiconductor substrate, forming a single-crystal semiconductor layer on the porous layer, forming a first two-dimensional circuit element on the single-crystal semiconductor layer, bonding the first two-dimensional circuit element to a support substrate and then removing the semiconductor substrate from the bonded body so as to transfer the first two-dimensional circuit element from the semiconductor substrate to the support substrate, and bonding the support substrate to which the first two-dimensional circuit element is transferred to a substrate having a second two-dimensional circuit element.
The three-dimensional circuit element manufacturing method described in Japanese Patent Laid-Open No. 11-17107 will be described below.
First, as shown in FIG. 5A, a porous layer 2 is formed on a semiconductor substrate by anodizing. A single-crystal silicon layer 3 is formed on the porous layer 2.
As shown in FIG. 5B, a first two-dimensional LSI 4 is formed on the single-crystal silicon layer 3 formed on the porous layer 2. The two-dimensional LSI 4 includes an element isolation oxide film 5, MOSFET 6, polysilicon interconnection 7, interlayer dielectric film 8, via hole 8a, upper surface metal interconnection 9, and interlayer dielectric film 10.
As shown in FIG. 5C, polyimide 11 is applied to the surface of the two-dimensional LSI 4. A support substrate 12 is bonded to the polyimide 11.
As shown in FIG. 5D, the two-dimensional LSI 4 supported by the support substrate 12 is separated from a single-crystal silicon substrate 1.
As shown in FIG. 5E, a through hole 13 that reaches the polysilicon interconnection 7 is formed in the single-crystal silicon layer 3 and element isolation oxide film 5 on the lower surface side of the peeled two-dimensional LSI 4. An oxide film 14 is formed in the through hole 13. The oxide film 14 is partially removed by etching to expose the polysilicon interconnection 7 again. A lower surface metal interconnection 15 which comes into contact with the polysilicon interconnection 7 is formed. Polyimide 16 is applied. An Au/In pool 17 is formed in the recessed portion of the lower surface metal interconnection 15.
On the other hand, as shown in FIG. 5F, a porous silicon layer 22 and single-crystal silicon layer 23 are formed on another single-crystal silicon substrate 21 in the same way as described above. A two-dimensional LSI 24 is formed on the single-crystal silicon layer 23. The two-dimensional LSI 24 includes an element isolation oxide film 25, MOSFET 26, polysilicon interconnection 27, interlayer dielectric film 28, via hole 28a, upper surface metal interconnection 29, interlayer dielectric film 30, via hole 30a, and tungsten plug 31.
As shown in FIG. 5G, the upper surface of the two-dimensional LSI 24 shown in FIG. 5F is bonded to the lower surface of the two-dimensional LSI 4 shown in FIG. 5E via the polyimide 16 and 30.
In the same way as in FIG. 5D, the two-dimensional LSIs 4 and 24 are separated from the single-crystal silicon substrate 21.
When a necessary number of thin-film two-dimensional LSIs each formed on a single-crystal silicon layer are sequentially bonded in the above-described way, a desired three-dimensional VLSI can be completed.
In the above-described three-dimensional LSI manufacturing method, the two-dimensional LSI 4 formed on the porous layer 2 is bonded to the support substrate 12. After that, the two-dimensional LSI 4 supported by the support substrate 12 is separated from the single-crystal silicon substrate 1. A semiconductor process is executed for the separation surface to form the lower surface metal interconnection 15. The surface of the two-dimensional LSI 24 formed on another single-crystal silicon substrate 21 is bonded to the lower surface metal interconnection 15. After that, the support substrate 12 is removed by polishing or etching. That is, the layer formation process is complex.